A novel SRAM with SET and RESET functions using a novel 5-input majority gate in quantum-dot cellular automata (QCA) technology

Abstract In the nanoscale VLSI industry, Quantum-dot Cellular Automata (QCA) presents a novel substitute for conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology. This paper introduces a new design that uses QCA technology. The design includes a 5-input Majority Gate (5-MG), a fundamental component in QCA, and a Static Random Access Memory (SRAM) cell with set and reset features. The recommended design offers a minimum clock cycle, a small QCA layout area, less cost function, and a sustainable arrangement to get the ideal size and latency while consuming less power. The proposed 5-input majority gate (MG) has a total area of 0.009 μm 2 and a QCA cell count of 14. Further, a novel SRAM cell is implemented using the 5-input MG logic. The SRAM cell designed using 44 QCA cells has a clock latency of 1 and a layout area of 0.03 μm 2 . Compared to the conventional 5-MG SRAM cell the proposed 5-MG SRAM cell shows a 50% reduction in cell counts and a 62.5% reduction in total layout area.