Investigation of Ways of Synthesizing Concurrent Error-Detection Circuits Based on Boolean Signal Correction Using Uniform Separable Codes

The features of the synthesis of concurrent error-detection circuits (CEDCs) based on Boolean signal correction (BSC) using uniform separable codes are studied. Three types of structures are considered: type I, a structure with correction of part of the signals from the outputs of the diagnostic object forming the check symbols of the given code in the CEDC; type II, a structure with correction of part of the signals from the outputs of the diagnostic object forming the data symbols of the given code in the CEDC; and type III, a structure with signal correction from all outputs of the diagnostic object. For structures of all types, formulas are given for determining the number of ways of synthesizing CEDCs based on BSC using the given code. New properties of structures are established that characterize the features of the growth in the number of methods for synthesizing CEDCs with an increase in the number of outputs forming the data and check symbols. Patterns are found that allow in practice estimating the number of ways of synthesizing CEDCs based on BSC using uniform separable codes in order to select the best one according to the specified criteria. Examples are given to demonstrate the effectiveness of using the found patterns.