Impact of deep and tail trap states on the electrical performance of double-gate ZnO thin film transistors

Abstract Traps in ZnO thin film transistors (TFTs) affect the electrical characteristics of the device. Traps originate primarily due to the disordered nature of the deposited semiconductor channel or are present at the ZnO and gate-dielectric interface. This work studies the effect of traps in double-gate ZnO TFTs using technology computer-aided design. The grain boundary and interface traps are assumed to be localized at the ZnO/SiO 2 interface and are defined within the energy bandgap of ZnO using a double-exponential function. The traps are assumed to be of the acceptor type. The concentration of tail states is assumed to be 10 3 times more than in the deep state, while the characteristic temperature of deep state traps is assumed to be higher than the tail states. In common mode operation (i.e. both top and bottom gates are shorted), the tail states dominate the device characteristic compared with the deep state, while in independent mode (i.e. both gates are biased independently) the deep state traps affect the device characteristics more than the tail states.