Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π- Type Filtering Structure

In this article, we studied the phenomenon of test failures in CLK phase noise assessment, identifying the antiresonance in the power supply network of clock chip. We found that the jitter of the CLK signal is strongly correlated with the filtering effect of the power supply network of the clock chip. To improve the jitter performance of CLK signal, we implemented a n-type filtering structure into the existing circuit topology. This modification successfully mitigated the antiresonance peak. In order to minimize jitter as much as possible, we have optimized and compared the n-type filtering structure from simulation and test perspective. Finally, we have provided a general conclusion regarding this issue.