Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI)

This paper proposes the extended scale cache (ESC) stacked-graphics processing unit (GPU)-high bandwidth memory (HBM) module architecture. The main concept of the proposed architecture involves stacking an ESC, which is an L2 cache, atop a GPU to decrease off-chip data movement, thereby reducing power consumption and latency. However, the simultaneous switching noise (SSN) of the proposed architecture is increased due to additional switching noise transferred from the ESC to the GPU cores, leading to degraded power integrity (PI) performance. To ensure stable PI performance of the proposed architecture, we design and analyze the hierarchical power distribution network (PDN) of the proposed architecture and the simultaneous switching current (SSC) for both the GPU and ESC. Additionally, we conduct modeling and analysis of the SSN of the proposed architecture. By employing decoupling capacitors (decaps) with a total capacity of 1,152 nF, the SSN of the proposed architecture is reduced to 7.65 mV, which is 0.695% of the supply voltage (VDD), demonstrating that the proposed architecture guarantees reliable PI performance.