Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate

In recent years, high-performance and chiplet-type CPUs need futher improvements of their performance. It is necessary for the chiplet-to-chiplet communication to increase the throughput. The issue of improving the throughput in UCIe communication is that the large number of required substrate layers makes the interposer expensive. This paper proposes a new design method to implement UCIe wiring, typically using two layers, with a single layer to achieve cost-effective interposers. We adjusted the UCIe form factor rules to the single-layer wiring and identified the need for fine-pitch wiring as 10 μm or less. In addition, to reduce crosstalk in the wiring between dies, we proposed a wiring layout that increases the wiring pitch only between dies. We modeled the interposer, conducted a signal integrity analysis, and confirmed that communication at the transmission rate of 32 Gbps is possible over die-to-die distances of 1–10 mm. We concluded that the interposer cost reduction of about 40 % is feasible using single-layer UCIe wiring.