PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements

This paper estimates and analyzes the power supply noise induced jitter (PSIJ) caused by system-level power noises in high-capacity PCI express (PCIe) Gen 6.0 SSDs. To guide optimal design of the hierarchical power distribution network (PDN) with consideration of PSIJ before mass production, a measurement-based jitter sensitivity function (JSF) is employed during the PCle PHY IP chip-level verification stage. For accurate JSF measurement, it must be ensured that the 64 Gbps PAM-4 eye of the PCle interface is open during operations. In this paper, we propose a test architecture that can measure signal jitter with PAM-4 eyes opened while removing decoupling capacitors (de-caps) at the off-chip level so that single tone power noise applied to the off-chip test point (TP) can be transmitted safely to the on-chip stage without filtering. Using a hierarchical PDN model of the proposed test architecture, JSF was extracted in the 300 kHz to 300 MHz frequency range, considering the voltage transfer ratio (VTR) from TP to the target die bump. We confirmed, for the first time, that PSIJ caused by worst-case system power noise in a high-capacity PCle Gen 6.0 SSD operating at full performance is estimated to be 1.32 ps, which corresponds to 42.2 % of the eye width specification of the PCle Gen 6.0 base specification.