A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects
Designing high-speed interconnects faces challenges from factors like jitter, noise, and skew, which degrade performance. This study introduces a 155 MHz low-jitter PLL clock generator using CMOS 180 nm model files. Operating with a 10 MHz reference signal input, it achieves 2.832 ps average jitter, crucial for signal integrity in high-speed interconnects.
Authors
- Tee Hui Teo (ORCID: https://orcid.org/0000-0003-2123-9347)
- Mulat Ayinet Tiruye
- Olani Baissa Gerba
Institutions
- University of Pisa (IT)
- Singapore University of Technology and Design (SG)
- Engineering (Italy) (IT)
Publication Details
- Published
- 2024-10-06
- DOI
- https://doi.org/10.1109/epeps61853.2024.10754287
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00