Yield-Aware Interposer Design for UCIe Interconnects
This work presents an interposer design methodol-ogy for UCle die-to-die interfaces that maximizes yield given a set of signal integrity specifications. Four different routing configurations on a silicon interposer are considered, and the cost, performance, and yield tradeoffs are elucidated. The fabrication steps for the D2D interconnects are outlined and sources of yield-limiting variability are identified. The yield analysis is expedited by the use of a Gaussian Process Regression surrogate model.
Authors
- Ashita Victor (ORCID: https://orcid.org/0000-0002-0062-1128)
- Elyse Rosenbaum (ORCID: https://orcid.org/0000-0002-3919-9833)
- Nam Sung Kim (ORCID: https://orcid.org/0000-0002-0442-5634)
- Muhannad S. Bakir (ORCID: https://orcid.org/0000-0002-0380-0842)
- Ram Krishna
- Srujan Penta
- Xu Chen (ORCID: https://orcid.org/0000-0002-7670-0164)
Institutions
- Georgia Institute of Technology (US)
- University of Illinois Urbana-Champaign (US)
Publication Details
- Published
- 2024-10-06
- DOI
- https://doi.org/10.1109/epeps61853.2024.10753661
- Citations
- 1
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.21
Funders
- National Science Foundation