A Signal Integrity Comparison of VIPPO Technology for PCIe 5.0 DC Blocking Capacitors

This work studies the signal integrity effects of VIPPO-style vias and DC blocking surface-mount capacitors required by many high-speed serdes interfaces, focusing on PCIe 5.0 transmitters. A test vehicle was built containing four via-and-capacitor configurations fixtured with coaxial probe contacts, as well as a calibration structure for broadband de-embedding. Passive measurements are discussed, and de-embedding is attempted. A set of 3D full-wave models are built that validate the reliability of de-embedded results after post-processing. The 0201-capacitor seated on VIPPO vias performs the best against the demonstrated tests from a high-speed signal integrity standpoint.