Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging

In this paper, the analysis of a controlled structuration approach of the silicon (Si) substrate surface roughness through standard acidic wet chemical etching is proposed for the first time, for silver-based backside metallization (BSM) in power electronics packaging applications. Periodically spaced circular openings with diameters and separation distances from 1 um to 5 um were patterned using maskless laser lithography and wet etched in a Si substrate with a standard acidic HNP (HF: HNO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>:H<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>PO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf>) mixture for 30s. The etched cavities were characterized by scanning electron microscopy (SEM). The extracted etching parameters from SEM observations were used to implement simple analytical models for the estimation of the average arithmetic surface roughness R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</inf>and the normalized etching depth (with respect to the opening's diameter after etching) as a function of the circular openings' dimensions, separation distance and the corresponding underetch. Roughness values ranging from 165 nm to 555 nm were estimated depending on the design specifications. A good correlation was observed between the experimental and theoretical values of the normalized etching depth. The introduced approach allows a rapid estimation of the surface roughness after etching without the need for photoresist removal for profilometry or AFM measurements, which makes it suitable for both rapid prototyping as well as for additional etching cycles after SEM if needed.