BioPI: An Energy Efficient and Low-Latency Neuromorphic Pipelined System With Joint Design Optimizations of Sensor-Algorithm-Processor for Wearable Healthcare
Extensive research has been conducted on accurate classification of bio-signals for wearable healthcare applications, such as the detection of arrhythmia. Artificial Intelligence (AI) based methods utilizing dedicated neural networks (NN) have shown potential in classifying multi-class bio-signals. However, the separate designs of processors and sensors has introduced interaction overheads in existing studies, limiting their practicality and efficiency. Furthermore, there is a lack of detailed discussion on the joint design and optimization of bio-signal sensing, NN training, and NN acceleration. To address these challenges in wearable healthcare, this work proposes an efficient and low-latency neuromorphic system, BioPI, from a joint design perspective of sensor, algorithm, and processor. Inspired by biological neural systems, BioPI employs fully-spike dataflow with a hierarchical pipelined architecture, combining a mixed-signal analog-to-spike converter (ASC) and a compact pipelined spiking neural network (SNN) processor with event-triggered power gating. A unique duplicate-merge (DM) SNN algorithm is also presented to optimize the processing of ASC generated data during inference by converting the required SNN structures from 2-D to 1-D, which reduces on-chip memory size and operation numbers for inference by 2.02x and 1.98x, respectively, measured on ECG classification task while maintaining state-of-the-art accuracy. To validate the system functionality, we built an end-to-end verification platform including a fabricated 40nm ASC chip and a FPAG implementation of the SNN processor. To evaluate the overall energy efficiency of the entire system on silicon, a complete design of BioPI is also implemented in 40nm process and post-layout simulations are conducted. In arrhythmia detection tasks using the MIT-BIH ECG dataset, BioPI achieves an overall accuracy of 97.5% in 4-class classification and an energy efficiency of 0.767uJ/classification, with a merely 12.54us execution latency.
Authors
- Jie Yang (ORCID: https://orcid.org/0000-0002-4148-0042)
- Fengshi Tian (ORCID: https://orcid.org/0000-0003-1304-5593)
- Jingyu He (ORCID: https://orcid.org/0000-0003-0370-8867)
- Chaoming Fang (ORCID: https://orcid.org/0000-0001-8830-1294)
- Chi-Ying Tsui (ORCID: https://orcid.org/0000-0002-8024-2637)
- Kwang‐Ting Cheng (ORCID: https://orcid.org/0000-0002-3885-4912)
- Yao Yuan (ORCID: https://orcid.org/0000-0001-9849-2290)
- Hui Wu (ORCID: https://orcid.org/0009-0001-4079-068X)
- Mohamad Sawan (ORCID: https://orcid.org/0000-0002-4137-7272)
- Xiaomeng Wang (ORCID: https://orcid.org/0000-0003-2169-3013)
- Jiakun Zheng (ORCID: https://orcid.org/0009-0007-8602-9451)
- Jinbo Chen (ORCID: https://orcid.org/0000-0001-6202-9165)
Institutions
- Hong Kong University of Science and Technology (HK)
- Westlake University (CN)
- University of Hong Kong (HK)
Publication Details
- Journal
- IEEE transactions on circuits and systems for artificial intelligence.
- Published
- 2024-11-21
- DOI
- https://doi.org/10.1109/tcasai.2024.3502573
- Citations
- 2
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.42