TCAD Design of a 3-Terminal Inverter Using Non-Align Double Gates and Its Performance Assessment

This work presents the design and simulation analysis of a compact nano-scale single-device inverter structure of 220 nm length and an oscillator by using non-aligned double gate MOS technology. The proposed non-aligned double gate inverter (NADGI) structure is a three-terminal device compared to the conventional four-terminal double gate field effect transistor. The performance of the NADGI was tested using two gate oxide materials: silicon dioxide (SiO2, k = 3.9) and hafnium dioxide (HfO2, k = 24), showing improved results in terms of delay, power consumption, and energy efficiency, especially with low-k materials. The voltage-gains of NADGI with low-k, and high-k materials are, –14 and –21 V/V, respectively. NADGI with low-k materials results in lower values for noise margin high (0.47 V), and noise margin low (0.397 V). By using the graphical method, the optimal supply voltage of the NADGI was determined and is nearly 0.65 V. At optimal supply voltage with 1 GHz signal, and CL = 10 fF, the NADGI with low-k gate oxide gives tp = 6.2 ps, EDP = 0.25 fJ-ps, PDP = 44.6 aJ, high-k gate oxide gives tp = 7 ps, EDP = 0.44 fJ-ps, PDP = 64.46 aJ. Simulation results indicate that NADGI with low-k materials performs better at high frequencies and lower power consumption, while high-k materials are more suitable for driving large capacitors. Additionally, a 5-stage ring oscillator was tested at a supply voltage of 0.65 V. Under a load capacitance of 1 fF, the NADGI oscillator with low-k, and high-k gives an oscillation frequency of 25 and 16.6 GHz respectively. The simulation results show that NADGI with low-k gate oxide achieves higher oscillation frequencies compared to high-k materials.