Analysis and Mitigation of Excess Phase Noise and Spurs in Digital-to-Time-Converter-Enhanced Fractional- N Frequency Synthesizers

Digital-to-time converters (DTC’s) used in fractional-N phase locked loops (PLL’s) aim to zero the quantization error (QE) introduced by the divider controller in order to recover integer-N phase noise (PN) performance. Unfortunately, the inherent quantization behavior and integral nonlinearity associated with the DTC mean that the aforementioned QE cannot be canceled exactly; inevitably, the residual error gives rise to additional PN and spurious tonal phenomena. This tutorial paper uses DTC macromodels to analyze and distinguish the DTC’s sources of nonideality and the distinct adverse spectral responses induced by them. Different DTC enhancement techniques are shown to mitigate certain types of nonideality. A comprehensive design strategy incorporating these techniques is proposed, which mitigates the revealed excess PN and spurs introduced by the DTC’s nonidealities. The enhanced DTC enables the fractional-N DPLL to approach the fractional-spur-free integer-N PN performance limit. Behavioral simulations at both DTC-block and PLL-system levels confirm our analysis.