An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
Determining a channel’s characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver’s architecture. As the channel’s characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{5}$ </tex-math></inline-formula> times faster pulse acquisition rate than prior arts.
Authors
- Myungguk Lee (ORCID: https://orcid.org/0000-0002-5654-431X)
- Jaeik Cho
- Byungsub Kim (ORCID: https://orcid.org/0000-0003-1528-6235)
- Junung Choi (ORCID: https://orcid.org/0009-0005-1663-0140)
- Gain Kim (ORCID: https://orcid.org/0000-0002-3680-8816)
- Won Joon Choi (ORCID: https://orcid.org/0009-0008-9769-9263)
Institutions
- Pohang University of Science and Technology (KR)
- Daegu Gyeongbuk Institute of Science and Technology (KR)
- Samsung (South Korea) (KR)
Publication Details
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2024-11-21
- DOI
- https://doi.org/10.1109/tvlsi.2024.3497213
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Samsung