A 220-GHz LNA With 9.7-dB Noise Figure and 24.6-dB Gain in 40-nm Bulk CMOS

This brief proposes a low noise amplifier (LNA) with high gain at 220 GHz in bulk CMOS process. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\max }$ </tex-math></inline-formula>-core is employed to simultaneously realize noise and power matching as well as provide high gain. A segmented design methodology for LNAs in terahertz band is employed to trade-off gain and noise. Incorporating the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\max }$ </tex-math></inline-formula>-core with design methodology, a 220 GHz LNA is designed with balanced noise and gain performance. Fabricated using 40nm bulk CMOS process, measurement results reveal a minimum noise figure of 9.7 dB, a maximum gain of 24.8 dB between 214-225 GHz, and a saturated output power of −0.58 dBm at 220 GHz, while consuming only 36.9 mW. The LNA occupies a compact total area of 0.2 mm2, with a core area of 0.047 mm2. To the best of the authors’ knowledge, this represents the lowest noise figure achieved by LNA above 200 GHz using bulk CMOS technology.