Graph-Based Ranking Techniques for Improving VLSI Placement

In the physical design of Very Large-Scale Integration (VLSI) circuits, the placement process plays a critical role as it directly influences key design metrics such as power, performance, and area. Although substantial research has been conducted, the increasing complexity of VLSI designs continues to present challenges in achieving efficient and rapid placement. This paper provides a comprehensive review of placement optimization techniques, with a particular emphasis on accelerating VLSI physical design. Recent advancements in graph-based methods, such as graph clustering and GAN-Place utilizing Graph Neural Networks, have demonstrated significant potential. However, these approaches often overlook the critical importance of element weights within the graph. In this study, we evaluate the significance of ranking elements in a VLSI graph and introduce an optimized placement strategy based on this ranking, building upon DreamPlace. Our experimental results demonstrate that this approach enhances placement stage metrics and sustains these improvements through the post-route stage. Moreover, the proposed GraphBased Ranking method achieves a reduction in placement time by 2-6% compared to the conventional approach, without any noticeable difference in HPWL. By addressing the evolving challenges of modern VLSI placement, this research offers valuable insights and suggests future directions for optimizing placement in increasingly complex design environments.