LUT-Based Multipliers for IEEE-754 Floating Point Arithmetic on FPGAs

In the IEEE-754 standard for floating point arithmetic, multipliers with size 24-bits (single precision), 53-bits (double precision)), and 113-bits (quadruple precision) are required. LUTs (Look-Up Tables) are building blocks in FPGAs (Field Programmable Gate Arrays) which are used as accelerators for compute intensive applications. FPGAs include DSP Blocks with embedded hardwired multipliers. Lookup tables (LUTs) can be used to supplement the available on-chip multipliers. Delay and area are competing objectives in multiplier design. This paper describes the results of synthesizing 24-bits, 53/54-bits and 114bits multipliers using LUTs in FPGAs using a divide-and-conquer approach on the Xilinx Artix-7 with the Vivado 2020.2 synthesis tool. This approach is compared to the standard multiplier implementation in VHDL. Experimental results show that the divide-and-conquer approach has resulted in a 13.16% speed improvement with a 1.67% LUTs increase for the single precision. For the double precision, the speed has been reduced by 7.32% but the area has been reduced by 6.18% in terms of LUTs and by 28.14% in terms of registers. For the quadruple precision, the speed has been reduced by 20.41% but the area has been reduced by 9.28% in terms of LUTs and by 43.49% in terms of registers. Results show that by using the Karatsuba-Ofman’s approach, the area can be further reduced.