Compensation’s Method of Collector Load’s Parasitic Components in SiGe and SOI Cascode Amplifiers Operating at High Temperatures

This paper considers the circuit method for neutralizing the effect of parasitic components of the collector load in silicon-germanium (SiGe) and silicon-on-insulator (SOI) classical cascade amplifiers and common-base stages on their voltage gain (Gain). The article demonstrates that the incorporation of a dedicated compensating circuit into the original circuits enables the enhancement of their upper frequency limit or gain by a factor of 5 to 10. The conditions for mitigating the impact of resistor parasites, which contribute to losses in planar inductance, on the Q-factor of the RLC-circuit of the selective amplifier are established. It is recommended that the proposed circuit solutions be employed in practical applications involving SiGe and SOI analog chips operating at elevated temperatures.

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Publication Details

Published
2024-10-17
DOI
https://doi.org/10.1109/eexpolytech62224.2024.10755707
Primary Topic
Semiconductor Quantum Structures and Devices
Type
article
Field-Weighted Citation Impact
0.00

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article

Compensation’s Method of Collector Load’s Parasitic Components in SiGe and SOI Cascode Amplifiers Operating at High Temperatures

Yu. I. Ivanov, Anna V. Bugakova, Надежда Алексеевна Дмитриенко, Ilya V. Frolov
Semiconductor Quantum Structures and Devices
article

Compensation’s Method of Collector Load’s Parasitic Components in SiGe and SOI Cascode Amplifiers Operating at High Temperatures

Yu. I. Ivanov, Anna V. Bugakova, Надежда Алексеевна Дмитриенко, Ilya V. Frolov
article en

Abstract

This paper considers the circuit method for neutralizing the effect of parasitic components of the collector load in silicon-germanium (SiGe) and silicon-on-insulator (SOI) classical cascade amplifiers and common-base stages on their voltage gain (Gain). The article demonstrates that the incorporation of a dedicated compensating circuit into the original circuits enables the enhancement of their upper frequency limit or gain by a factor of 5 to 10. The conditions for mitigating the impact of resistor parasites, which contribute to losses in planar inductance, on the Q-factor of the RLC-circuit of the selective amplifier are established. It is recommended that the proposed circuit solutions be employed in practical applications involving SiGe and SOI analog chips operating at elevated temperatures.

Southern Federal University (RU), Don State Technical University (RU), Kotelnikov Institute of Radioengineering and Electronics of the Russian Academy of Sciences (RU)
Russian Science Foundation
Openalex Percentile: Top 81%
Semiconductor Quantum Structures and Devices
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