Systematic Topology Synthesis of Partial Power Processing Architecture

This paper investigates the systematic topology synthesis of PPP architecture. A topology synthesis method based on Buck-Boost is proposed, offering a new perspective for systematically explaining existing topologies. Additionally, a systematic naming method and a general expression set for voltage gain based on topology synthesis are introduced. Furthermore, new topologies are synthesized. Finally, the feasibility of the proposed topologies is verified using an exemplified case.