High-Speed Issues Mitigation of GaN Power Transistors Based on a New Gate Driving Profile

This paper presents a new gate-driving profile to mitigate the switching issues caused by high-speed operation of GaN transistors in on-off transitions. The concept consists of modifying the primary PWM signal applied to the GaN transistors to an appropriate voltage profile, which changes the gate-source voltage behaviour in the critical stage of the GaN transitions. The gate-driving concept is evaluated on LTspice, and the results show the reduction of ringing and overshoots when applying the proposal while maintaining tolerable power losses.