Super Cascode Circuit optimized for Electrical Testing at High Frequencies, Voltages and Voltage Gradients

Actual test systems for power electronic components face difficulties in efficiently managing the combination of high frequencies, high voltage amplitudes and steep voltage gradients, both from an economic and a technical standpoint. A novel solution to this challenge is the super cascode circuit, extensively discussed in various publications. [1], [2], [3], [4] The configuration of this system involves a series of interconnected semiconductor switches. In this research, the JFETs are based on SiC technology, offering a high breakdown voltage capability. This feature facilitates the optimization of the super cascode circuit for scenarios involving high voltages. In the context of the current project, improvements have been made to the parameters of a single super cascode circuit. Additionally, adjustments have been implemented to optimize the cascode for integration into a half-bridge setup.