Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective

Hybrid bonding plays an important role in advanced 2.5-D/3-D chiplet integration due to its distinctive advantages, such as higher interconnect density, lower power consumption, and better signal integrity. However, the dc/ac performance of the logic device in chiplet can be affected by the strain induced by the annealing and cooling steps of hybrid bonding. In this article, a coupled multiphysics simulation is performed to investigate the impact of the hybrid bonding process on the performance of p-type FinFET by introducing stress from the hybrid bonding process into quantum transport simulation for FinFET based on nonequilibrium Green’s function (NEGF) formalism, in which the impact of hybrid bonding process-induced stress on the band structure of the device is captured by employing six-band <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k} \cdot {p}$ </tex-math></inline-formula> Hamiltonian and deformation potential theory. The simulation results indicate that the on-state current and the hole density in the channel can be enhanced due to the variation of the density of states (DOSs) caused by hybrid bonding process-induced stress, the effect of process-induced stress on Y parameters and gate capacitance in the frequency domain is also explored. Devices near the center of copper pillars are more affected than those far away from the copper pillars. Decreasing the radius of copper pillars and annealing temperature or increasing the distance between copper pillars can decrease the hybrid bonding process-induced stress in FinFET, hence decreasing the change in device performance, including <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small>-state current, Y parameters, and gate capacitance.