Power Board Design for Parallel SiC MOSFET Characterization

The primary objective of this paper is to present the design of a power board specifically developed to investigate the impact of parameters and layout mismatches of paralleled SiC dies used in power modules. The layout of the half-bridge power board has been realized minimizing asymmetries among the parallel branches and including specific additional paths to modulate parasitic elements and decoupling resistances. In this way, current imbalance and differential-mode inter-chip oscillations can be investigated.