HfO₂–ZrO₂ Superlattice Ferroelectric Films as Gates for 2D MoS₂-Based Negative-Capacitance Transistors with Enhanced Subthreshold and Endurance Characteristics

A nanoscale ferroelectric film with a periodic 4 × [HfO2 (10 Å)-ZrO2 (5 Å)] superlattice (HZSL) structure was prepared with an optimal annealing temperature identified as 500 °C to achieve robust ferroelectric polarization and high endurance under a low thermal budget. This resulted in a 2Pr (two times remnant polarization) exceeding 50 μC/cm2 and a prolonged cycling endurance of 1010 cycles (2Pr > 40 μC/cm2). These properties are attributed to increased tensile strain from enhanced mechanical confinement due to the asymmetrical sublayer thicknesses in the HZSL film, which reduces the phase-transition barrier from tetragonal to orthorhombic phases (o-phase), forming a high concentration of ferroelectric o-phase in the HfO2 sublayer. A nanoscale gate stack comprising of 2 nm Al2O3 and 6 nm HZSL was integrated onto 2D MoS2 to fabricate a negative-capacitance field-effect transistor (NCFET) with channel lengths of 2 μm. The device demonstrated excellent performance, including an ultralow subthreshold swing (SS) of 28 mV/dec, minimal hysteresis (20 mV), and a high on/off current ratio of 107. These results are due to the enhanced negative-capacitance effect in the nanoscale HZSL film, superior HZSL/Al2O3 and Al2O3/MoS2 interface quality, and low defect density within the HZSL layer. Additionally, a negative drain-induced barrier lowering (DIBL) effect was observed, contrasting with conventional devices, resulting from the interaction among the polarized electric field, paraelectric field in the oxide, and drain-source and fringing electric fields. The MoS2 NCFET with 200 nm channel length displayed a low SS of 31 mV/dec and a negligible DIBL of −13 mV/V due to the enhanced polarization of the HZSL layer. This work is the first to report MoS2 NCFETs with an Al2O3/HZSL gate stack, showing that the HZSL film, with its low thermal budget, provides sufficient polarization and endurance for CMOS-compatible devices.