A 2.8 fJ/conversion-step 10-bit 500 kS/s SAR ADC with low-power switching scheme and dynamic comparator

A 10-bit 500 kS/s successive approximation register (SAR) analog-to-digital converters (ADCs) in 40-nm CMOS technology is presented in this paper. To reduce the power consumption of capacitive digital-to-analog converter (CDAC), a novel energy-efficient switching scheme is proposed without capacitor-splitting structure and additional Vaq reference. Considering the reset energy of 0.249 CV2ref, 94.93% switching energy saving and 75% total capacitor number reduction are achieved over the conventional switching technique. And the common mode voltage converges back to around Vcm by single-side switching up and then down. Furthermore, a low-power comparator is proposed based on the conventional double-tail architecture. The addition of the cross-coupled transistors avoids the unnecessary discharging of the pre-amplifier stage, decreasing 16.3% power consumption over the conventional architecture. Post-simulation results show the peak DNL/INL are +0.79/-0.28 LSB and +0.61/-0.57 LSB respectively. At 0.7 V supply, the proposed SAR ADC achieves an SNDR of 57.9 dB and an SFDR of 75.4 dB with Nyquist frequency. And the overall power consumption is 0.9047 μW, leading to a Walden’s figure of merit (FOMW) of 2.8 fJ/conversion-step.