3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

Abstract A new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO 2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 10 10 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

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Publication Details

Journal
Advanced Electronic Materials
Published
2024-11-19
DOI
https://doi.org/10.1002/aelm.202400438
Citations
5
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
1.04

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3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

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Advanced Electronic Materials
Ferroelectric and Negative Capacitance Devices
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article

3D Nano Hafnium‐Based Ferroelectric Memory Vertical Array for High‐Density and High‐Reliability Logic‐In‐Memory Application

Jiajie Yu, Jialin Meng, Hao Zhu, Zhenhai Li, Lu Chen, Qingqing Sun, Tianyu Wang, Lin Chen, Yongkai Liu, Kangli Xu, Yifan Song, David Wei Zhang
article en
5 citations

Abstract

Abstract A new type of ferroelectric memory device with high reliability and complementary metal‐oxide‐semiconductor (CMOS) compatibility characteristics is an important condition for achieving integrated memory and computing chips. Here, 3D stacked ferroelectric memory devices based on ferroelectric materials of HfO 2 are fabricated. The device exhibits high speed (50 ns), low read voltage (0.5 V), and great reliability with no substantial degradation after 10 10 cycles and a 10‐years data retention at 85 °C. The IMP and NAND logic are achieved with stable memory window (>200 mV) across the vertical devices’ interconnection. On this basis, combining with the traditional CMOS logic device, multiple combination logic functions containing NOT, AND, and NOR are achieved by simulation. The collaboration of devices in the vertical direction providing the possibility of combining multi‐bit logic in memory functions and paves the way for the implementation of high‐density, high‐reliability, and low‐energy consumption computing‐in‐memory chips compatible with the CMOS technology.

Advanced Electronic MaterialsVol. 11(4)
Shandong University (CN), Fudan University (CN), Shanghai Innovative Research Center of Traditional Chinese Medicine (CN), Shanghai Fudan Microelectronics (China) (CN)
National Natural Science Foundation of China, China Postdoctoral Science Foundation, Fudan University, Science and Technology Commission of Shanghai Municipality, Natural Science Foundation of Shandong Province, Key Program of NSFC-Tongyong Union Foundation, National Key Research and Development Program of China
Affordable and clean energy
Openalex Percentile: Top 22%
Ferroelectric and Negative Capacitance Devices
1.04
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