Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation

This paper proposes an FPGA implementation of Self-Rimed Ring Oscillator (STRO) based Time-to-Digital Converter (TDC). Thanks to the STRO features, this TDC is able to achieve a time resolution as fine as needed by simply increasing its number of stages. Even if the achievable time resolution is close to the tenths of picoseconds, the approach does not require a high frequency oscillator. This resolution is only limited by the STRO-stage noise in the FPGA. As a hardware proof-of-concept, this TDC has been implemented in a Cyclone IV FPGA to further confirm and evaluate the advantages of our proposed TDC architecture. Most of the measurements are perfectly in accordance with our theoretical claims.