Lightweight ANU-II Implementation on FPGA

As the application of Embedded devices in network communication increases exponentially, there is a growing necessity for effective security mechanisms that may be implemented within resource constraints. Lightweight cryptography becomes an essential solution, which includes constraints like latency, memory size, area, and power consumption. This study presents a hardware implementation of the ANU-II and Modified ANU-II block cipher using SPARTAN-6 Field Programmable Gate Arrays (FPGAs). The design presented has a 64-bit ANU-II and Modified ANU-II block cipher and offers comparison analysis with alternative data path architectures according to various design parameters. The FPGA-based solution additionally be reconfigured and is flexible, thereby making it appropriate for a variety of applications that require secure data transmission. The results demonstrate that the ANU-II and Modified ANU-II block cipher is not only high-performing but also flexible to various system needs. This research indicates how well our suggested encryption design may address the demands of current security concerns related to data. The result of the proposed ANU-II and Modified ANU-II algorithm shows a maximum frequency of 313.686 MHz and 316.131 MHz and delay of 3.188 ns and 3.163 ns respectively.