Investigating the Impact of Differential Voltage and Sense Amplifier Offset on Power and Delay of SRAM in 65nm LSTP Technology

Sense amplifier is a circuit that helps in the reading operation of the data stored in a memory array. In this paper, we have investigated the trade-off between the differential voltage on bit lines provided at the input of the sense amplifier with respect to the power and delay of the memory array. We observe that there is a decrease in the power of the memory array by 27.40%, 24.18%, and 17.33% for array configurations with 32, 64, and 128 rows, respectively if we increase the differential voltage of bit-lines provided to the sense amplifier. We also observe a decrease in delay by 23.70% and 14.20% with 32 and 64 rows, respectively. This technique is useful for applications with fewer rows in a memory array. The analysis is performed on input decoupled latch type sense amplifier for array configurations with 32,64,128,256 and 512 rows at 65 nm LSTP technology.