A Coarse Grained Reconfigurable Architecture for the Realization of Turbo Encoder

The class of programmable logic devices called as the coarse grained reconfigurable architectures (CGRAs) are becoming prominent because of their innate coarse grain reconfigurability and efficiency in terms of area and power. The reconfigurability of CGRAs surpasses their fine grain counter part and their area and power efficiency, matches with that of the ASICs. The reconfiguration in CGRA happens at word level, which reduces the reconfigurability time. Hardware realization of error correcting codes on FPGA platforms are reported in literature. These designs are computationally intensive and their realization on FPGAs comes at the cost of increased hardware usage, reconfiguration time, area occupancy and power consumption. CGRAs are evolving as a powerful platform for the realization of such computationally intensive kernels due to their array of functional units that can perform complex computations along with the efficient interconnect architecture. The focus of this work is to implement encoder design of turbo codes on CGRAs available in CGRA- Modelling and Exploration (ME) framework and explore the potential of the architectures for the realization of such designs. From this implementation study, a critical examination of the potential capabilities promised by CGRAs, towards the realization of encoders and decoders, is made. This has resulted in the design of a CGRA, that is more efficient for the realisation of turbo encoders, in terms of area occupancy, power consumption and usage of resources. It has been observed that the proposed architecture occupies 7.8% less area and consumes 8.1% less power than ADRES architecture in the CGRA-ME framework. Also, it occupies 34.36% less area and consumes 46.7% less power, when compared to the Simple architecture in the framework. These results show that CGRAs are a potential platform for realization of encoders and decoders for error correcting codes. With error correcting codes being an integral component of modern digital communication systems, this approach would pave the way for future exploration on the hardware realization of state of the art error correcting codes on CGRA platforms.