Power Optimization Techniques During Synthesis and Physical Design for a Low-Power RISC-V Design

With the proliferation of battery-operated systems, reducing power consumption in integrated circuits is increasingly critical. This paper introduces a comprehensive approach to reducing both static and dynamic power dissipation in the design of a Reduced Instruction Set Computer (RISC-V) processor, leveraging a unique combination of Synthesis and Physical Design techniques. The different power reduction approaches during synthesis are Optimizing constant flops, Gate merging, Pin swapping, Clock gating and Multiple supply voltage (MSV) synthesis. Techniques employed during Physical design is Gate sizing, Power-aware placement based on vectors, Removing buffers/inverters, Low-Power Clock Tree Synthesis (LP-CTS), Multi Threshold Voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{T}})$</tex> limplementation and Power Gating. These optimization techniques are applied to the design of a RISC-V and the results are compared with a non-optimized RISC-V design with respect to area, gates, power and slack. This design uses skywater130nm technology. This design and optimization is done using EDA tools Genus and Innovus from Cadence Design Systems. The novelty of this work is that we have accomplished significant reduction in area and power by using fully automated methods.