Implementation of High SNM SRAM Cell and Testing in 45 nm CMOS Logic Process

The persistent reduction in size and the increasing complexity of SRAM circuits have made them more susceptible to failures due to fluctuations in process parameters. These fluctuations significantly impair and severely degrade SRAM output. To improve this efficient SRAM cell and proper testing methodologies are required. This work presents a low-energy SRAM design cell. To address the poor Static Noise Margin (SNM) of previous memory cells, the proposed SRAM cell incorporates a pull-up PMOS and a high-threshold NMOS foot switch, ensuring cell stability even when the supply voltage is reduced. Additionally, a Positive Feedback Operational Amplifier Sensing (PFOS) circuit is integrated between bitlines (BL, BL) to minimize read delay and produce a full-swing output. Furthermore, a voltage mode select (VMS) circuit is added to each column to decrease the static power consumption of unselected cells, significantly reducing idle power. This is achieved by applying a lower voltage to maintain the state of the unselected cells. This work also presents a Hard-wired Built-in Self-Test (BIST) mechanism for detection of faults like transition faults occurring during write operations. The Hardwired BIST circuit's effectiveness was validated through simulations against faults in a 6T SRAM cell, designed in Cadence virtuoso using 45nm technology.