Design and Implementation of 32-bit RISC-V Processor Using Verilog

The design and implementation of a 32-bit single-cycle RISC-V processor in Verilog is a sophisticated and elaborate process that aims to create a functioning processor architecture that adheres to the RISC-V instruction set. To execute instructions in a single clock cycle, this research work requires the synthesis of components such as the program counter, register file, arithmetic logic unit (ALU), and memory modules. The Verilog-based implementation includes RISC-V instructions such as arithmetic, memory access, and control flow instructions. The design prioritizes simplicity and clarity, laying the groundwork for educational study and the eventual development of more advanced processing functionality. This emphasizes importance in understanding processor architecture and Verilog-based processor design.