An Efficient Method to Reduce Power in Built in Self Test

VLSI (Very Large Scale Integration) industry is at the forefront of technological innovation, continuously pushing the boundaries of chip design and fabrication to create increasingly powerful and efficient electronic devices. Its advancements drive the development of everything from smartphones and computers to IoT devices and automotive electronics, shaping the way we live and interact with technology. Circuit testing is crucial within the VLSI industry, wherein the output of a design is assessed against its performance. BIST (Built-In Self-Test) is a method that involves incorporating a Test Pattern Generator (TPG), Output Response Analyzer (ORA) and the main Design under Test (DUT) directly on to the chip. One of the challenges faced in in-circuit testing is the rise in power consumption. This work aims to generate deterministic patterns, such that it consumes less power while testing DUT. The TPG is developed for ISCAS'89 and EPFL benchmark circuits using Verilog. The proposed technique is synthesized using Synopsys Design Compiler. The percentage improvement in power when compared with Linear feedback shift register (LFSR), Read Only Memory (ROM) plus combinational circuit and binary counter based TPG is in the range of 7-99%, respectively.