Split Topology Based 8-Bit Flash ADC Architecture for Reduced Conversion Time

This paper presents the design of 8-bit flash ADC architecture using split based technique. The proposed design requires only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2(2^{N/ 2}-1)$</tex> number of comparators for N-bit of resolution and occupies only 30 comparators for 8-bit flash ADC instead of 255 comparators. The proposed architecture has resulted in less number of comparators due to split topology and incorporating intermediate stage in between. The ADC is designed on UMC 180nm CMOS technology and obtains the conversion time and power dissipation of only 3.46ns and 110mW respectively at 1.8V power supply.