An FPGA Accelerator Design of Spiking Neural Network for Energy-Efficient Object Detection

Recently, spiking neural network (SNN) has shown remarkable performance in a variety of applications, ranging from elementary tasks like image classification to more intricate challenges such as object detection. The SNN draws considerable attention because it shows lower energy consumption than the previous artificial neural network (ANN). However, the existing spiking-based object detection model, such as spiking-YOLO, is still too large to achieve real-time processing on the Field Programmable Gate Array (FPGA). In this paper, an energy-efficient FPGA accelerator design of the SNN is proposed for object detection. This work concentrates on both algorithm optimization and hardware architecture design. In algorithm optimization, channel pruning and batch-normalization fusion are adopted to reduce the ANN complexity. Then, a scale-aware pseudo-quantization method is proposed to reduce the model size further, and continuous inference neurons are proposed to accelerate SNN inference. In hardware design, fully pipelined architecture and systolic array are proposed to accelerate the SNN computation. The experimental results show that our optimized network achieves 26 times model size reduction at similar detection accuracy, and the hardware results show that our architecture can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256\times 256$ </tex-math></inline-formula>@681fps real-time processing under 150MHz working frequency on the FPGA platform.