A Power-Efficient Core Micro-Architecture Based on RISC-V Instruction Set Architecture

RISC processors have become a dominant force in processor design due to their simplicity and efficiency. One such architecture, RISC-V, offers a powerful yet streamlined instruction set, making it a popular choice for embedded systems. This paper delves into the design of a RISC processor with a particular focus on optimizing the power consumption of the Arithmetic Logic Unit (ALU). Since multipliers are known to be the most power-hungry components within an ALU, the paper proposes a redesign of the multiplier's internal circuitry using suitable alternatives. Specifically, the design utilizes the Baugh-Wooley algorithm for signed multiplication due to its efficiency. Furthermore, the paper details how the internal circuit of this multiplier is redesigned to minimize both power consumption and area footprint, ultimately leading to a more energy-efficient system overall. By focusing on optimizing the power-hungry multiplier within the ALU, this design approach aims to reduce the overall power consumption of the RISC-V processor significantly. The proposed system is implemented in Verilog HDL. The proposed design optimizes the area and power by reducing 18.5% and 7.4% respectively when compared to the existing system.