A 200-MS/s 12-b Cryo-CMOS CS DAC for Quantum Computing

This brief presents a 200 MS/s 12 bits cryogenic CMOS (cryo-CMOS) current steering (CS) digital to analog converter (DAC) designed to operate from 300K down to 4 K. The DAC is designed and simulated using a 110nm cryo-CMOS SPICE model, achieving practical performance at 4K. Mismatch in transistor threshold voltage, carrier mobility and layout at cryogenic temperature can lead to unpredictability and incorrect bias voltage, so an off-chip resistor current mirror structure was adopted for the bias circuit. Due to the flexible configuration of the off-chip resistance value and the PMOS current source, this bias structure has certain advantages in overcoming the extended cryogenic nonlinear and mismatch effects to get the correct bias voltage at 4K. This DAC is implemented in a 110nm CMOS process, with a core area <<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.21{mm}^{2}$ </tex-math></inline-formula>. With 9mA full-scale output current, this DAC consumes less than 22mW at 4K. The SFDR achieves 57.94dB, 48.59dB, and 35.33dB at 4.76MHz, 43.67MHz, and 93.47MHz frequency of full swing output, respectively, at 200MS/s and 4K, and the differential and integral nonlinearity are 0.79 LSB and 3.81 LSB, respectively, at 4K.