Novel parallel inputs shift registers with set/reset terminals in QCA nanotechnology

This paper was focused on logic gates, D-latch, parallel-parallel shift-registers, and parallel-series shift registers, which are used as basic circuits in numerous circuits as well as computational and comparative units. To design proposed shift registers, D-latch which is the vital gate, is designed carefully for minimum size, decreasing number of cells and good performance for delay. The proposed level-sensitive parallel-in parallel-out (<i>PIPO</i>) shift registers with reset terminal and with both set and reset terminals (single-layer and multi-layer), edge-sensitive <i>PIPO</i> shift registers with reset and set/reset abilities (single-layer and multi-layer), and the parallel-in serial-out (<i>PISO</i>) shift registers were designed using the proposed D-latches. Simulations show that the proposed level-sensitive <i>PIPO</i> shift-register set and reset terminals has <i>145 QCA</i> cells, <i>0.</i>13 μm² occupied area, and delay of about <i>1.25</i> cycles of QCA clock. In addition, the proposed edge-sensitive <i>PIPO</i> shift-register circuit with set-and-reset pins has <i>163 QCA</i> cells, <i>0</i>.17 μm² occupied area, and delay of about <i>1.25</i> cycles of QCA clocks. All designs and simulation results were made in the QCADesigner software.