Temperature Compensation in FD-SOI Transistors: A Novel Approach with 27% Performance Improvement via Parasitic Diode Biasing

This paper presents an innovative technique to reduce the temperature dependency of transistors. This technique relies on Back-Gate and parasitic diodes biasing, exploiting the Complementary To Absolute Temperature (CTAT) behavior of diodes' threshold voltage. Ideas and work presented in this paper are based on the Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The proposed technique is validated through a test bench mimicking real-world conditions. The results show that the proposed technique can effectively reduce temperature dependency.