Compact hardware implementation of ZUC algorithm for NB-IoT

The Internet of Things (IoT) domain is currently facing unavoidable and persistent challenges in the form of cybersecurity threats and constrained device resources. To address the aforementioned issues, this paper designs an efficient low-area hardware implementation of the ZUC algorithm on an ASIC platform, utilizing time-multiplexing and clock gating techniques. This circuit minimizes area by ensuring that each functional module is instantiated only once. In the design of the S-box, this paper draws on the concept of tower field decomposition and proposes an algorithm to search for isomorphic mapping matrices between the finite field mathbbF2^nand the finite field mathbbF2^n^prime. The algorithm aims to find an isomorphic mapping that, when multiplied by the affine matrix of the S-box operation and other related matrices, can achieve the mapping with the least number of XOR logic gates. Based on these two points, the implemented S1-box in this paper has an area comparable to the current AES algorithm's S-box. In the linear transformation part, the paper adopts the idea of maximum distance separable (MDS) matrix decomposition, allowing the entire linear layer to be implemented with only 164 XOR gates. For the design of the addition chain, the paper employs a carry-save adder, a 32-bit adder, a single operand 31-bit adder, and intermediate registers. This design enables the linear feedback shift register layer and the finite state machine layer to share the same addition chain, further optimizing the circuit structure. The proposed hardware implementation achieves a throughput of 2 Gbps at a clock frequency of 250 MHz, with an area overhead of only 6.67 kGE, under the TSMC 90 nm process. Compared to current mainstream designs, this paper reduces area overhead by 44% while maintaining the same throughput.