Application of UVM Methodology to Modeling Precision Digital Signal Processing Devices

The purpose of the article is to analyze the Universal Verification Methodology (UVM) approach and develop its modification for modeling precision digital signal processing devices as part of periodic signal phase meters. The article proposes a partial implementation of UVM techniques and methods based on general-purpose programming languages, which is distinguished by the presence of a subsystem for metrological evaluation of the characteristics of the simulated measuring device, while the UVM approach, implemented in the Accelera class library in the System Verilog language, assumes the presence of a reference response with which comparison is made. Thus, the proposed approach, while preserving the methodological basis of UVM, allows modifying it for use in systems where the reference response is not assumed, since it is the subject of the study.