A novel partitioned hybrid PWM strategy to reduce the common‐mode voltage in three‐level neutral‐point‐clamped inverters

Abstract To reduce the common‐mode voltage (CMV) generated during the operation of the three‐level neutral‐point‐clamped (3L‐NPC) inverters, this study proposes a partitioned hybrid pulse width modulation (PHPWM) strategy. In this strategy, the three‐level vector space is divided into high‐modulation region and low‐modulation region according to the modulation index. The reference voltage is synthesized by only medium and small basic vectors with low CMV magnitude. In the low‐modulation region, a clamped level method and a five‐segment asymmetric switching sequence are adopted to reduce the loss and current distortion. In the high‐modulation region, it repartitions the vector space by medium vectors and takes a seven‐segment asymmetric switching sequence to reduce the loss and distortion slightly. The simulation results for the PHPWM strategy and the other two strategies are compared to demonstrate the superiority of PHPWM. The experiment results verify its feasibility. The results indicate that the PHPWM is capable of restricting the CMV within 1/6 of the DC‐linkage voltage and it can make a balance between efficiency and output total harmonic distortion.