FPGA Implementation of Compact Architecture for Lightweight Hash Algorithm for Resource Constrained Devices

The security implications of the emerging world of smart devices brought about by the Internet of things' recent rise are enormous. IoT devices typically have restricted resources, such as minimal memory, low processing power, and a short battery life, in addition to their stated security level. In the context of IoT, lightweight cryptographic primitives are presented taking into account the trade-off between speed and security assurance. In this research, we proposed lightweight cryptographic hash methods and optimized hardware for devices with limitations. The size, speed, efficiency, and power consumption of our suggested solutions are examined on FPGA systems. Bit permutation, linear transformation, and S-Box functionality are used in the suggested design. To analyze large data sets and Internet of Things applications, conventional hash algorithms need memory and time. Thus, the demand arises for a lightweight cryptographic protocol that is both rapid and safe. This technique offers the necessary security criteria of conventional hash functions and the parameters for lightweight cryptographic protocols. The proposed architecture is tested and validated based on three key criteria: memory, speed, and power consumption, which are important factors in determining its lightweight nature. Based on the findings, the proposed architecture outperforms other lightweight protocols regarding memory usage, performance, and power consumption. For an appropriate FPGA-based application deployment, a thorough comparison of our suggested designs is detailed on various FPGA families.