Improvement of Memory Window of Silicon Channel Hf₀.₅Zr₀.₅O₂ FeFET by Inserting Al₂O₃/HfO₂/Al₂O₃ Top Interlayer

In this work, we propose a gate structure to enhance the memory window (MW) of Si-channel Hf0.5Zr0.5O2 FeFETs. We achieve an MW of 10.04 V by inserting an Al2O3/HfO2/Al2O3 (AHA) top dielectric interlayer between the ferroelectric Hf0.5Zr0.5O2 layer and the metal gate, where the gate-stack thickness is 14.8 nm. The physical origin is that the Al2O3/HfO2, HfO2/Al2O3, and Al2O3/Hf0.5Zr0.5O2 interfaces can trap charges from the metal gate, contributing to the MW enhancement. This AHA top dielectric multilayer effectively suppresses charge loss compared with a single Al2O3 top dielectric interlayer. Moreover, the de-trapping of charges injected from the metal gate is the primary factor for the degradation of the MW in this structure. Our work provides a guide for improving the MW of FeFET.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2024-11-15
DOI
https://doi.org/10.1109/ted.2024.3489595
Citations
9
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
1.88

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article

Improvement of Memory Window of Silicon Channel Hf₀.₅Zr₀.₅O₂ FeFET by Inserting Al₂O₃/HfO₂/Al₂O₃ Top Interlayer

Tianchun Ye, Runhao Han, Kai Han, Saifei Dai et al.
9 citations
IEEE Transactions on Electron Devices
Ferroelectric and Negative Capacitance Devices
1.88
article

Improvement of Memory Window of Silicon Channel Hf₀.₅Zr₀.₅O₂ FeFET by Inserting Al₂O₃/HfO₂/Al₂O₃ Top Interlayer

Tianchun Ye, Runhao Han, Kai Han, Saifei Dai, Wenwu Wang, Xiaoqing Sun, Tao Hu, Junshuai Chai, Xianzhou Shao, Mingkai Bai, Xiaolei Wang, Yajing Ding, Jia Yang, Hao Xu
article en
9 citations

Abstract

In this work, we propose a gate structure to enhance the memory window (MW) of Si-channel Hf0.5Zr0.5O2 FeFETs. We achieve an MW of 10.04 V by inserting an Al2O3/HfO2/Al2O3 (AHA) top dielectric interlayer between the ferroelectric Hf0.5Zr0.5O2 layer and the metal gate, where the gate-stack thickness is 14.8 nm. The physical origin is that the Al2O3/HfO2, HfO2/Al2O3, and Al2O3/Hf0.5Zr0.5O2 interfaces can trap charges from the metal gate, contributing to the MW enhancement. This AHA top dielectric multilayer effectively suppresses charge loss compared with a single Al2O3 top dielectric interlayer. Moreover, the de-trapping of charges injected from the metal gate is the primary factor for the degradation of the MW in this structure. Our work provides a guide for improving the MW of FeFET.

IEEE Transactions on Electron DevicesVol. 71(12)
Chinese Academy of Sciences (CN), Institute of Microelectronics (CN), Weifang University (CN)
National Natural Science Foundation of China, Natural Science Foundation of Shandong Province
Openalex Percentile: Top 14%
Ferroelectric and Negative Capacitance Devices
1.88
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