SRAM With Oxide Semiconductor Pull-Down Transistors on the Backside Enabling Full-Node PPA Improvement
The 6T SRAM bitcell, consisting of four pFETs on the same tier and two oxide-semiconductor pull-down transistors stacked on the backside, can achieve 17% power reduction, 32% performance enhancement, and 42% area reduction as compared to one-tier SRAM bitcell. With the high strength ratio of the pass-gate transistors to the pull-down transistors, near-threshold-voltage write reduces the minimum operating voltage.
Authors
- Hsin-Cheng Lin (ORCID: https://orcid.org/0000-0002-2110-4867)
- Tien‐Chen Liu (ORCID: https://orcid.org/0000-0001-6771-5025)
- Tao Chou (ORCID: https://orcid.org/0009-0003-3872-3466)
- C. W. Liu (ORCID: https://orcid.org/0000-0002-6439-8754)
- Li-Kai Wang
- Ching-Wang Yao
- Tsai-Yu Chung
Institutions
- National Taiwan University (TW)
Publication Details
- Journal
- IEEE Electron Device Letters
- Published
- 2024-11-15
- DOI
- https://doi.org/10.1109/led.2024.3498840
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Science and Technology Council