Fast & Safe IO Memory Protection

IO Memory protection mechanisms prevent malicious and/or buggy IO devices from executing errant transfers into memory. Modern servers achieve this using an IOMMU---IO devices operate on virtual addresses, and IOMMU translates virtual addresses to physical addresses (potentially speeding up translations using a cache called IOTLB) before executing memory transfers. Despite their importance, design of memory protection mechanisms that can provide strong safety properties while achieving high performance has remained elusive. Indeed, recent studies from production datacenters demonstrate that inefficiencies within state-of-the-art memory protection mechanisms result in significant throughput degradation, orders-of-magnitude tail latency inflation, and violation of isolation guarantees.

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Publication Details

Published
2024-11-04
DOI
https://doi.org/10.1145/3694715.3695943
Citations
1
Primary Topic
Security and Verification in Computing
Type
article
Field-Weighted Citation Impact
0.35

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article

Fast & Safe IO Memory Protection

Rachit Agarwal, Qizhe Cai, Benny Rubin, Saksham Agarwal
1 citations
Security and Verification in Computing
0.35
article

Fast & Safe IO Memory Protection

Rachit Agarwal, Qizhe Cai, Benny Rubin, Saksham Agarwal
article en
1 citations

Abstract

IO Memory protection mechanisms prevent malicious and/or buggy IO devices from executing errant transfers into memory. Modern servers achieve this using an IOMMU---IO devices operate on virtual addresses, and IOMMU translates virtual addresses to physical addresses (potentially speeding up translations using a cache called IOTLB) before executing memory transfers. Despite their importance, design of memory protection mechanisms that can provide strong safety properties while achieving high performance has remained elusive. Indeed, recent studies from production datacenters demonstrate that inefficiencies within state-of-the-art memory protection mechanisms result in significant throughput degradation, orders-of-magnitude tail latency inflation, and violation of isolation guarantees.

Urbana University (US), Cornell University (US)
National Science Foundation
Openalex Percentile: Top 32%
Security and Verification in Computing
0.35
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Fast & Safe IO Memory Protection — Rachit Agarwal, Qizhe Cai, et al. · (2024) | TGRS Research Map | TGRS