Design and Comparative Analysis of on-Chip CMOS Oscillators

The paper evaluates three inverter-based ring oscillator architectures: basic inverter based, current-starved, and dual-latch based designs. It analyzes key metrics like oscillation frequency, stability, power consumption, phase noise, and power spectrum characteristics through simulations. Despite the dual- latch design offering improved stability, it consumes more power. The study provides insights into phase noise and power spectrum characteristics, aiding designers in making trade-offs for their applications. Simulations were conducted in Cadence Virtuoso using UMC 180nm technology, showing all architectures achieving a 1 MHz oscillating frequency at 1.8V supply voltage.