Area and Power Optimized RTL to GDS II Flow of a Telecommunication Receiver Core

The Register Transfer Level (RTL) to Graphic Design System II (GDS II) flow is pivotal in any integrated circuit (IC) design. The work outlines the process of IC design from RTL to GDS II, leveraging Cadence EDA tools: Genus for logic synthesis and Innovus for physical design implementation. As a case study, a telecommunication receiver core implemented using Verilog code is considered. Key components of the receiver core are a phase-locked loop for clock generation, a signal processing core for real-time signal processing, and a power manager for efficient distribution. These are essential for telecommunication signal decoding in applications such as telephone dialing and interactive voice response systems. The paper aims at optimizing design parameters for performance, area, and power, ensuring reliability and meeting application demands. The synthesis step transforms high-level descriptions into gate-level representations, optimizing for various metrics, while physical design implementation ensures efficient placement, routing, and clock distribution. Evaluation of timing and power characteristics facilitates cost reduction and chip area optimization. The study proposes optimization of area, timing, and power. The optimization results emphasize a reduction in cell area by 1730 um<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, an increase in positive slack value by 33%, and a total power reduction of 25%. All optimization techniques were implemented using Cadence's Genus and Innovus.